As CMOS technology improves, the need for interfacing between 3 and 5 volt systems has increased. Some prior art embodiments utilize NMOS pull-up devices. A common loading configuration occurs when an output driver (hereafter referred to as "OD") is driven by a 3V power source and drives another 5 volt chip. For example, when the OD is operated in a high impedance state (in this disclosure, a "high impedance state" of the OD is considered to be a state wherein the OD neither sinks or sources significant current to the output node)--A high impedance state of the OD in the prior art embodiments is accomplished by turning both the pull-up and the pull-down transistors off, the gate of the NMOS pull-up device is at ground and the drain is clamped at 5 Volts. This condition provides a voltage spread (in this disclosure, the term "voltage spread" is taken to be synonymous with "voltage difference" or "voltage differential") between the source and the gate of up to 5 volts for the above conditions in the prior art configuration. The resulting high electric field can be very detrimental to the gate oxide especially in those instances where the NMOS transistors are being configured with relatively thin gate oxides. As a result, during normal operation of such systems, the lifetimes and reliability of the NMOS pull-up devices and the ODs may be diminished.
The present invention is partially concerned with limiting the voltage differential between the gate and the source to some level which will increase the life of the NMOS pull-up device (transistor), such as may occur during high impedance state. This is one of the primary features of the present invention. It is envisioned that the present invention may be useful to all CMOS chip manufacturers making logic and memory chips.